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Digital design (Fall 2005) |
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| Course code : | IDIG1A-U01 | ||
| ECTS Credits : | 10 | Status : | Compulsory |
| Revised : | 29/08 2005 | Written : | 27/05 2005 |
| Placement : | 1. semester | Hours per week : | 8 |
| Length : | 1 semester | Teaching Language : | Danish |
| Objective : | Be able to describe, design and test as well as implement combinational and synchronous sequential digital circuits using truth tables and state diagrams. Be able to use the development software tool for synthesis and test. | ||
| Principal Content : | Binary and hexadecimal number systems, Boolean algebra, truth tables, combinational circuits, flip-flops, sequential circuits including counters and state machines. Programmable logic devices (PLD). VHDL-program structure for combinational and sequential digital circuits including state machines Structural design using block diagrams and/or structural VHDL description. Test combinational and sequential digital circuits using test benches. | ||
| Teaching method : | The teaching is a combination of class teaching and exercises. The teaching is based on a number of assignments which are carried out in groups. | ||
| Required prequisites : | - | ||
| Recommended prerequisites : | - | ||
| Relations : | - | ||
| Type of examination : | Oral examination based on assignments | ||
| External examiner : | Internal | ||
| Marking : | Scale of 13 | ||
| Remarks : | Some assignment exercises is done during the semester. The module is finished by an oral examination. Admission to the examination will depend upon the assignment exercise journals being delivered on time. The exam is an group exam with individual mark. The mark is based on a general impression about how good the level is in relation to the objective for the module and the handed in journals, the oral presentation and the functionality for each design. The group starts by presenting the points and or problem from the final written assignment exercise as each student makes a well-prepared oral presentation. Each student presentation must only take 5 minutes. The group is required to coordinate the presentations in such a way that the major aspects of the assignments are covered, that the presentations are different and that each individual presentation has a good technical span. After the presentation the supervisors and the external examiner pose questions inspired by the presentations and the written journals for all course assignments. The questions are a priori individual but may - if found relevant by the supervisors or the internal examiner - form the basis of a broader group discussion. During the evaluation by the supervisors and the external examiner, the project group leaves the room. Afterwards the group is summoned and the individual marks are explained. If the student doesn’t pass the examination, the student is given guidance on how to improve the chances of passing. XILINX WebPack is used as a tool for designing digital electronics |
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| Teaching material : | Digital Electronics, dig1a and dig2a. Pearson. Prentice Hall. | ||
| Responsible teacher : | Ole Schultz
, osch@dtu.dk |
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