Dansk - English
Kort version - Fuld version
VHDLE (Forår 2007) |
|||
| Kursuskode : | EVHDLE-U01 | ||
| ECTS Point : | 7,5 | Status : | Tilvalg for den valgte retning |
| Placering : | 5-7 semester | Timer pr. uge : | 4 |
| Længde : | 1 semester | Undervisningssprog : | Dansk |
| Hovedindhold : | The structure of VHDL: - lexical description and syntax. - design units, control structures, data objects and instructions. - subprograms Model description: - behavioral og structural domain models. - abstraction hierarchy and data transfer. Simulating - script - testbench Design, simulations and implementation of a basic CPU The course is based on WebPack version 9.1i.design tools |
||
| Undervisningsform : | The teaching is a combination of class teaching and exercises. The teaching is based on a course project, which is done in groups. | ||
| Krævede forudsætninger : | Dokumenteret viden svarende til DIG1A og DIG2A. | ||
| Ansvarlig underviser : | Mogens Pelle
, mpel@dtu.dk |
||