Dansk - English
Short version - Full version
VHDLE (Spring 2008) |
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| Course code : | EVHDLE-U01 | ||
| ECTS Credits : | 7,5 | Status : | Optional for specified Programme |
| Placement : | 5-7 semester | Hours per week : | 4 |
| Length : | 1 semester | Teaching Language : | Danish |
| Principal Content : | The structure of VHDL: - lexical description and syntax. - design units, control structures, data objects and instructions. - subprograms Model description: - behavioral og structural domain models. - abstraction hierarchy and data transfer. Simulating - script - testbench Design, simulations and implementation of a basic CPU The course is based on WebPack version 9.1i.design tools |
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| Teaching method : | The teaching is a combination of class teaching and exercises. The teaching is based on a course project, which is done in groups. | ||
| Required prequisites : | Basic VHDL (Dig1A/Dig2A) | ||
| Responsible teacher : | Mogens Pelle
, mpel@dtu.dk |
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