Dansk - English
Short version - Full version
Digital Electronics 3 (Fall 2004) |
|||
| Course code : | EDEL3-U01 | ||
| ECTS Credits : | 5 | Status : | Compulsory |
| Revised : | 26/01 2004 | Written : | 11/06 2001 |
| Placement : | 3. semester | Hours per week : | 4 |
| Length : | 1 semester | Teaching Language : | Danish and English |
| Objective : | The aim of the study module is to make the student able to - use a structural design method - configure FPGA components - use a softwarebased development tool to configure the FPGA - use simulation as tool for functional and timings behaviour of the digital design | ||
| Principal Content : | The module will contain the following topics: FPGA architecture. Combinational and synchronous circuits described in VHDL and implemented into the FPGA. Simulation of FPGA design with the use of Test Bench. | ||
| Teaching method : | The teaching is a combination of going through theory and doing exercises. The teaching is built upon a number of exercises and assignments which are carried out in groups. | ||
| Required prequisites : | Documented knowledge similar to DEL2. | ||
| Recommended prerequisites : | - | ||
| Relations : | - | ||
| Type of examination : | Oral examination based on assignments | ||
| External examiner : | Internal | ||
| Marking : | Scale of 13 | ||
| Remarks : | In order to sit for the examination the assignments must be handed in in time and approved by the teacher. The group enters the examination together. If the course is not passed an individual guidance is given the the student in order to improve the student"s chances of passing the examination next time. XILINX"s Foundation ISE or WebPack is used as a development tool. Menthor Graphics ModelSim is used as simulation tool. | ||
| Teaching material : | Mark Zwolinski: Digital System Design with VHDL | ||
| Responsible teacher : | Ole Schultz
, osch@dtu.dk |
||