Dansk - English
Kort version - Fuld version
VHDLE (Forår 2013) |
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| Kursuskode : | EVHDLE-U01 | ||
| ECTS Point : | 7,5 | Status : | Tilvalg for den valgte retning |
| Revideret : | 30/04 2013 | Oprettet : | 29/08 2003 |
| Placering : | 5. -7. semester | Timer pr. uge : | 4 |
| Længde : | 1 semester | Undervisningssprog : | Dansk hvis der ikke er engelsksprogede studerende tilstede |
| Målsætning : | To enable the student to develop VHDL-models for simulations, synthesis and implementation. The main project is to implement a model first as a behavioural model and later refine this model to a RTL structural model which can be synthesised. The design is then tested in a Xilinx FPGA. | ||
| Hovedindhold : | The structure of VHDL: - lexical description and syntax. - design units, control structures, data objects and instructions. - subprograms Model description: - behavioral og structural domain models. - abstraction hierarchy and data transfer. Simulating - script - testbench Design, simulations and implementation of a basic model The course is based on WebPack version 12 or later design tools |
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| Undervisningsform : | The teaching is a combination of class teaching and exercises. The teaching is based on a course project, which is done in groups. | ||
| Krævede forudsætninger : | Digital Electronics 1 and Digital Electronics 2 or equivalent | ||
| Anbefalede forudsætninger : | - | ||
| Relationer : | - | ||
| Prøveform : | Mundtlig evaluering på grundlag af kursusopgaver | ||
| Censur : | Intern | ||
| Bedømmelse : | 7-trinsskala | ||
| Bemærkninger : | Some assignment exercises are done during the semester. In order to sit for the examination the reports must be approved by the teacher. In the beginning of the semester the students form their own project groups. The group size should be 3-5 students. Each group pick up a test-board in the workshop Before the exam: Group presentation of the project. Each student will give a 5 minutes presentation of a part of the project. These presentations must be different and together they must cover important topics of the project. Oral exam: The exam is individual, and allow 10 minutes pr. student. The assessment is based on a general impression of the student with respect to the goals of the course. This will be evaluated from the project report, the oral performance as well as the functionality of the project. During the exam supervisor and censor will ask questions inspired by the presentation and the project report. After the exam: If the student doesn’t pass the examination, the student is given guidance on how to improve the chances of passing. |
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| Undervisningsmateriale : | Notes. Supplement: The Designers Guide to VHDL 2nd edition. Peter J. Ashenden. ISBN 1-55860-674-2. Morgan Kaufmann Publishers |
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| Ansvarlig underviser : | |||